tag:blogger.com,1999:blog-10741332530237869972024-03-12T17:23:24.928-07:00nee-ASIC DesignAll About
VLSIEngineering
(BackEnd-Physical Design-Place and Route)G. Partha Sarathihttp://www.blogger.com/profile/10982368947051776900noreply@blogger.comBlogger8125tag:blogger.com,1999:blog-1074133253023786997.post-7801601291047239882011-03-31T01:07:00.000-07:002011-04-14T09:41:21.481-07:00Standard Cell Rows on Core and RUF<div dir="ltr" style="text-align: left;" trbidi="on"><div class="separator" style="clear: both; text-align: center;"></div><div class="separator" style="clear: both; text-align: center;"></div><div class="separator" style="clear: both; text-align: left;"><span style="font-size: large;">The area allotted for standard cells on the core is known as standard cell area. This area is divided into the rows known as standard cell rows as shown in the below figure.</span></div><div class="separator" style="clear: both; text-align: left;"><span style="font-size: large;"><img border="0" height="444" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiTxy4vz5IoB0hUQVcVmAGA7TBoP1BRFyKLkbzr-i3j2B7W_YTgMcH2yIDZS-ESKb_IYr_zmjCNG3PuGra61jno_iLAlE80LqAYMfxkupz8i9pAufbsGXarinAd1tOOwgYH8C5sw8-brRs/s640/rows.bmp" width="640" /></span></div><span style="font-size: large;">The height of this row is equal to the height of the standard cell. In digital designs most of the cases, the height of standard cells are constant and width varies. There may be double height cells , triple height cell, etc. Similarly the rows also have heights accordingly. The standard cells will sit in the row with proper orientation.</span><br />
<span style="font-size: large;">The rows may abut or may not. The abutted rows share the power connections ( Will be explained in the Power Planning).</span><br />
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<span style="font-size: large;">To be continued ....</span><br />
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<span style="font-size: large;"><iframe align="left" frameborder="0" marginheight="0" marginwidth="0" scrolling="no" src="http://rcm.amazon.com/e/cm?t=n0c3f-20&o=1&p=8&l=bpl&asins=0387938192&fc1=000000&IS2=1&lt1=_blank&m=amazon&lc1=0000FF&bc1=000000&bg1=FFFFFF&f=ifr" style="height: 245px; padding-right: 10px; padding-top: 5px; width: 131px;"></iframe><br />
</span></div>G. Partha Sarathihttp://www.blogger.com/profile/10982368947051776900noreply@blogger.com1tag:blogger.com,1999:blog-1074133253023786997.post-3471743439065693062011-03-28T05:53:00.000-07:002011-04-14T09:42:49.622-07:00Aspect Raio of Core/Block/Design<div dir="ltr" style="text-align: left;" trbidi="on"><span style="font-size: large;">The Aspect Ratio of Core/Block/Design is given as:</span><br />
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<div class="separator" style="clear: both; text-align: center;"><span style="font-size: large;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjQDa4-oFg3Pi5hWlGSCGfS7tBEyt7AMTI-gaXPCvEMgDncntJIGo5Q2yjrwY8W-N1SwoR7YfstmTECOOd61bzgaXlnwzXWKG9wXPbA42I9-dqXo973lEgxEhMEKkJfiyPBB2MzjdjLd0o/s1600/AspectRatio_formula.bmp" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="52" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjQDa4-oFg3Pi5hWlGSCGfS7tBEyt7AMTI-gaXPCvEMgDncntJIGo5Q2yjrwY8W-N1SwoR7YfstmTECOOd61bzgaXlnwzXWKG9wXPbA42I9-dqXo973lEgxEhMEKkJfiyPBB2MzjdjLd0o/s320/AspectRatio_formula.bmp" width="320" /> </a></span></div><div class="separator" style="clear: both; text-align: left;"><br />
</div><div class="separator" style="clear: both; text-align: left;"><span style="font-size: large;">The aspect ratios of different core shapes are given in below :</span></div><div class="separator" style="clear: both; text-align: left;"><br />
</div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: large;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj4lUqbHiF7nHbU86xIbuJwRmVY8eq0H_YyAC4-pnBrdtAcgUNwhSWWEJOwENHm-Crzm473Eo_LciR7z2-67pcRIou1Rm_zUBew7d9nABIVkDMsMrand4X9Ks_K7BlPzV2ahi2F7nhoaHs/s1600/AspectRatio.bmp" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="476" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj4lUqbHiF7nHbU86xIbuJwRmVY8eq0H_YyAC4-pnBrdtAcgUNwhSWWEJOwENHm-Crzm473Eo_LciR7z2-67pcRIou1Rm_zUBew7d9nABIVkDMsMrand4X9Ks_K7BlPzV2ahi2F7nhoaHs/s640/AspectRatio.bmp" width="640" /></a></span></div><div class="separator" style="clear: both; text-align: left;"><span style="font-size: large;"><br />
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<span style="font-size: large;">The Role of Aspect Ratio on the Design:</span><br />
<ul style="text-align: left;"><li><span style="font-size: large;">The aspect ratio effects the routing resources available in the design</span></li>
<li><span style="font-size: large;">The aspect ratio effects the congestion </span></li>
<li><span style="font-size: large;">The floorplanning need to be done depend on the aspect ratio</span></li>
<li><span style="font-size: large;">The placement of the standard cells also effect due to aspect ratio</span></li>
<li><span style="font-size: large;">The timing and there by the frequency of the chip also effects due to aspect ratio</span></li>
<li><span style="font-size: large;">The clock tree build on the chip also effect due to aspect ratio</span></li>
<li><span style="font-size: large;">The placement of the IO pads on the IO area also effects due to aspect ratio</span></li>
<li><span style="font-size: large;">The packaging also effects due to the aspect ratio</span></li>
<li><span style="font-size: large;">The placement of the chip on the board also effects</span></li>
<li><span style="font-size: large;">Ultimately every thing depends on the aspect ration of core/block/design</span></li>
</ul><span style="font-size: large;">The all the points are drawn attention in future articles</span><br />
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<span style="font-size: large;"><a href="http://www.amazon.com/Physical-Design-Essentials-Khosrow-Golshan/dp/0387515224?ie=UTF8&tag=n0c3f-20&link_code=btl&camp=213689&creative=392969" target="_blank"><iframe align="left" frameborder="0" marginheight="0" marginwidth="0" scrolling="no" src="http://rcm.amazon.com/e/cm?t=n0c3f-20&o=1&p=8&l=bpl&asins=144194219X&fc1=000000&IS2=1&lt1=_blank&m=amazon&lc1=0000FF&bc1=000000&bg1=FFFFFF&f=ifr" style="height: 245px; padding-right: 10px; padding-top: 5px; width: 131px;"></iframe>Physical Design Essentials</a><img alt="" border="0" height="1" src="http://www.assoc-amazon.com/e/ir?t=n0c3f-20&l=btl&camp=213689&creative=392969&o=1&a=0387515224" style="border: medium none ! important; margin: 0px ! important; padding: 0px ! important;" width="1" /><br />
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</span></div>G. Partha Sarathihttp://www.blogger.com/profile/10982368947051776900noreply@blogger.com3tag:blogger.com,1999:blog-1074133253023786997.post-48322772848338593232011-03-28T01:59:00.000-07:002011-03-28T05:54:08.599-07:00Floor Planning in P and R Flow - Part2<div dir="ltr" style="text-align: left;" trbidi="on"><style>
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<div class="MsoNormal"><span style="font-size: large;">Continued from <a href="http://neeasic.blogspot.com/2011/03/floor-planning-in-p-and-r-flow.html">Part1</a></span> <br />
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<span style="font-size: large;">The Floorplanning is the first step in the ASIC P and R flow. The following terminologies are required to understand before proceeding further in to the Floorplanning process.</span></div><ul style="margin-left: 120px; text-align: left;"><li><span style="font-size: large;"><a href="http://neeasic.blogspot.com/2011/03/aspect-raio-of-coreblockdesign.html">Aspect Ratio</a> of Core or Block or Design</span></li>
<li><span style="font-size: large;">Standard Cell Rows</span></li>
<li><span style="font-size: large;">RUF (Row Utilization Factor)</span></li>
<li><span style="font-size: large;">Congestion</span></li>
<li><span style="font-size: large;">Blockages – Placement and Routing</span></li>
<li><span style="font-size: large;">Guide, Region and Fence</span></li>
</ul><div class="MsoNormal"><span style="font-size: large;"><br />
</span></div><div class="MsoNormal"><span style="font-size: large;">The major part of the Floorplanning is the Deciding the Chip/Block/Design size and placing the macros over the core area. Before proceeding into the Die size calculations understand the Die area and its components.</span></div><div class="MsoNormal"><span style="font-size: large;">The die area is divided in to the following areas:</span></div><div class="MsoNormal"><span style="font-size: large;"><br />
</span></div><ul style="margin-left: 120px; text-align: left;"><li><span style="font-size: large;">Core area / Core Box</span></li>
<li><span style="font-size: large;">IO area / IO Box</span></li>
<li><span style="font-size: large;">Channel between the Core and IO area</span></li>
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<div class="MsoNormal"><div class="separator" style="clear: both; text-align: center;"><span style="font-size: large;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi1czInO2y6EDdoml1exFiQhBHUb9A1ynu_S4IBhWtnxtocKd6KNbhB1pRZY5WJLAopvTJuD7G-_Cx8GPmV0mij4jo5CXY06J5YSB7WNASiMaRvyzDNtjdIosC3TLP_jTCTu1yUFkJUyLY/s1600/die1.bmp" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi1czInO2y6EDdoml1exFiQhBHUb9A1ynu_S4IBhWtnxtocKd6KNbhB1pRZY5WJLAopvTJuD7G-_Cx8GPmV0mij4jo5CXY06J5YSB7WNASiMaRvyzDNtjdIosC3TLP_jTCTu1yUFkJUyLY/s320/die1.bmp" width="320" /></a></span></div><span style="font-size: large;"><br />
</span></div><div class="MsoNormal"><span style="font-size: large;">The die consists of the number of IO pads and Corner pads in the IO area, and non or one or more Hard Macros (PLL, RAM, ROM, etc.) and Standard Cells (Flip Flops, NAND, NOR, AOI, etc.) in the core area.</span><br />
<div class="separator" style="clear: both; text-align: center;"><span style="font-size: large;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhCLoKxvBk9-PfvINbAr5TJSzB_2nsaSlGMxJIkWZPtmPWaTa2KI-aI0zaNY0JsQfUEWZXqRO_odE0JnOhZr9cpKd9-Hb2ouLfnEKu77TeuACIgLPZGIyHJY7h0pTvWdAP3UXxblvkKE7g/s1600/die2.bmp" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhCLoKxvBk9-PfvINbAr5TJSzB_2nsaSlGMxJIkWZPtmPWaTa2KI-aI0zaNY0JsQfUEWZXqRO_odE0JnOhZr9cpKd9-Hb2ouLfnEKu77TeuACIgLPZGIyHJY7h0pTvWdAP3UXxblvkKE7g/s320/die2.bmp" width="320" /></a></span></div><br />
<span style="font-size: large;">The core logic consist the standard cells and had macros. The IO pads are the interfaces circuits between Core logic and the IO pins present on the IC package. The IC pins are used to connect and mount the IC on a PCB or board.</span><br />
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<span style="font-size: large;">The core area is allotted for Macros and Standard Cells. The Standard Cell area is divided into the number of standard cell rows.</span></div><div class="MsoNormal" style="margin-left: 0.5in;"><span style="font-size: large;"><br />
</span></div><div class="MsoNormal" style="margin-left: 0.5in;"><span style="font-size: large;">(Will be Continued in Part3.....Die Size Calculation)</span></div></div>G. Partha Sarathihttp://www.blogger.com/profile/10982368947051776900noreply@blogger.com1tag:blogger.com,1999:blog-1074133253023786997.post-67611615040582619312011-03-23T02:38:00.000-07:002011-03-28T02:02:02.850-07:00Floor Planning in P and R Flow<div dir="ltr" style="text-align: left;" trbidi="on"><style>
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<div class="MsoNormal"></div><div class="MsoNormal" style="text-indent: 0.5in;"><span style="font-size: large;">Floorplanning is the art of any physical design. A well thought-out floorplan leads to an ASIC design with optimum area and high performance.</span></div><div class="MsoNormal" style="text-indent: 0.5in;"><span style="font-size: large;"><br />
</span></div><div class="MsoNormal" style="text-indent: 0.5in;"><span style="font-size: large;">After importing the design into the P&R tools with all libraries and design netlist, floorplan is performed.</span></div><div class="MsoNormal" style="text-indent: 0.5in;"><span style="font-size: large;"><br />
</span></div><div class="MsoNormal" style="text-indent: 0.5in;"><span style="font-size: large;">Floorplanning is nothing but placing the blocks /macros on the core area or another block after deciding the size of the block or core/die, thereby defining the standard cell areas between the macros/blocks.</span></div><div class="MsoNormal" style="text-indent: 0.5in;"><span style="font-size: large;"><br />
</span></div><div class="MsoNormal" style="text-indent: 0.5in;"><span style="font-size: large;">We will create and develop a physical model of the design in the form of an initial optimized layout.</span></div><div class="MsoNormal" style="text-indent: 0.5in;"><span style="font-size: large;"><br />
</span></div><div class="MsoNormal" style="text-indent: 0.5in;"><span style="font-size: large;">The following tasks are done during flooring planning.</span></div><div class="MsoNormal" style="margin-left: 1in; text-indent: -0.25in;"><span style="font-size: large;">1.</span><span style="font: large "Times New Roman";"> </span><span style="font-size: large;">Deciding the size of the core/die or block</span></div><div class="MsoNormal" style="margin-left: 1in; text-indent: -0.25in;"><span style="font-size: large;">2.</span><span style="font: large "Times New Roman";"> </span><span style="font-size: large;">Deciding the IO pads locations</span></div><div class="MsoNormal" style="margin-left: 1in; text-indent: -0.25in;"><span style="font-size: large;">3.</span><span style="font: large "Times New Roman";"> </span><span style="font-size: large;">Placing the Macros at appropriate place on the core</span></div><div class="MsoNormal" style="margin-left: 1in; text-indent: -0.25in;"><span style="font-size: large;">4.</span><span style="font: large "Times New Roman";"> </span><span style="font-size: large;">Placing any floorplan constrains like placement blockages, routing blockages, macro halos, etc., on the core area</span></div><div class="MsoNormal" style="margin-left: 1in; text-indent: -0.25in;"><span style="font-size: large;">5.</span><span style="font: large "Times New Roman";"> </span><span style="font-size: large;">Fixing the placement of standard cells of particular module on the core area</span></div><div class="MsoNormal" style="margin-left: 1in; text-indent: -0.25in;"><span style="font-size: large;">6.</span><span style="font: large "Times New Roman";"> </span><span style="font-size: large;">Deciding the continuous area for standard cell placement</span></div><div class="MsoNormal" style="margin-left: 0.5in;"><span style="font-size: large;">The above tasks are performed based on the connectivity available in the netlist.</span><br />
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</span></div><div class="MsoNormal" style="margin-left: 0.5in;"><span style="font-size: large;">Optimization of the layout is in terms of reducing the chip area, reducing the total net length, improving the timing there by increasing the operating frequency, resolving congestion there by maximizing the routability, reducing the crosstalk noise effects, reducing the power consumption, etc.</span><br />
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<span style="font-size: large;">To be continued in <a href="http://neeasic.blogspot.com/2011/03/floor-planning-in-p-and-r-flow-part2.html">Part2</a>....... </span></div></div>G. Partha Sarathihttp://www.blogger.com/profile/10982368947051776900noreply@blogger.com1tag:blogger.com,1999:blog-1074133253023786997.post-27313497083599576842011-03-18T05:03:00.000-07:002011-03-18T05:08:24.958-07:00Yield of Integrated Circuits<div dir="ltr" style="text-align: left;" trbidi="on"><div style="font-family: Times,"Times New Roman",serif;"><style>
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</style> </div><div class="MsoNormal"><span style="font-size: large;">The fabrication of ICs is a complex process and involves many chemical, mechanical, electrical, optical variables. Hundreds of ICs are manufactured on a single wafer at a time and the wafers are created in lots. </span></div><div class="MsoNormal"><span style="font-size: large;">The integrated circuits are called die (<i>die is singular as well as plural</i>) when they are on a wafer and called chips when they are separated from the wafer. </span></div><div class="MsoNormal"><span style="font-size: large;">The die are tested in different methods for its intended functionality, characteristics and parameters like frequency, power consumption, temperature, etc. All die are not up to the mark after manufacturing. Among the reasons to discard a die are wrong resistance, an open circuit, a missing conductor, and being physically too large or too small in some dimension. <o:p></o:p></span></div><div class="MsoNormal"><span style="font-size: large;">Yield is the fraction goods of chip among the total number chips manufactured. The total number may be total chips of a single wafer or total chips of a lot. The yield analytically:</span></div><div class="MsoNormal"><br />
</div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh-9dAwJBX4Fn0CGzGg134oWpMWXrP6-6hBBRvg-u85uFkxnNcRXF9fY_NKD3s6_itGop77RNBowFavIGUqFf42lwHTaTFWlYE7T5VJdpuferx5wDRNvhpc6ab3gp0JnQWpksnh5br8RtA/s1600/yield.bmp" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="54" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh-9dAwJBX4Fn0CGzGg134oWpMWXrP6-6hBBRvg-u85uFkxnNcRXF9fY_NKD3s6_itGop77RNBowFavIGUqFf42lwHTaTFWlYE7T5VJdpuferx5wDRNvhpc6ab3gp0JnQWpksnh5br8RtA/s320/yield.bmp" width="320" /></a></div><div class="MsoNormal"><span style="font-size: large;"><o:p></o:p></span></div></div>G. Partha Sarathihttp://www.blogger.com/profile/10982368947051776900noreply@blogger.com2tag:blogger.com,1999:blog-1074133253023786997.post-11898392482911320062011-03-18T03:23:00.000-07:002011-03-18T05:06:40.461-07:00VLSI Design Flow -2<div dir="ltr" style="text-align: left;" trbidi="on"><div style="font-family: Times,"Times New Roman",serif;"><style>
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</style> </div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;">Start reading from <a href="http://neeasic.blogspot.com/2011/03/vlsi-design-flow.html">VLSI Design Flow -1</a> </span><br />
<br />
<span style="font-size: large;">Physical design is performed with respect to design rules that represent the physical limitations of the fabrication medium. For instance, all wires must be a prescribed minimum distance apart and have prescribed minimum width. As such, the design layout must be recreated in (migrated to) each new manufacturing technology.<o:p></o:p></span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;"><br />
</span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;">Physical design directly impacts circuit performance, area, reliability, power, and manufacturing yield. Examples of these impacts are discussed below.<o:p></o:p></span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;"><br />
</span></div><ul style="font-family: Times,"Times New Roman",serif; margin-top: 0in;" type="disc"><li class="MsoNormal"><span style="font-size: large;"><b>Performance:</b></span><span style="font-size: large;"> long routes have significantly longer signal delays.<o:p></o:p></span></li>
<li class="MsoNormal"><span style="font-size: large;"><b>Area:</b></span><span style="font-size: large;"> placing connected modules far apart results in larger and slower chips.<o:p></o:p></span></li>
<li class="MsoNormal"><span style="font-size: large;"><b>Reliability:</b></span><span style="font-size: large;"> large number of vias can significantly reduce the reliability of the circuit.<o:p></o:p></span></li>
<li class="MsoNormal"><span style="font-size: large;"><b>Power:</b></span><span style="font-size: large;"> transistors with smaller gate lengths achieve greater switching speeds at the cost of higher leakage current and manufacturing variability; larger transistors and longer wires result in greater dynamic power dissipation.<i><o:p></o:p></i></span></li>
<li class="MsoNormal"><span style="font-size: large;"><b><a href="http://neeasic.blogspot.com/2011/03/yield-of-integrated-circuits.html">Yield</a>:</b></span><span style="font-size: large;"> wires routed too close together may decrease yield due to <i>electrical shorts </i></span><span style="font-size: large;">occurring during manufacturing, but spreading gates too far apart may also undermine yield due to longer wires and a higher probability of <i>opens</i></span><span style="font-size: large;">. <br />
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<o:p></o:p></span></li>
</ul><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;">Due to its high complexity, physical design is split into several key steps:<o:p></o:p></span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;"><br />
</span></div><ul style="font-family: Times,"Times New Roman",serif; margin-top: 0in;" type="disc"><li class="MsoNormal"><span style="font-size: large;"><b><i>Partitioning</i></b><b><i>:</i></b></span><span style="font-size: large;"> Breaks up a circuit into smaller subcircuits or modules which can each be designed or analyzed individually.<o:p></o:p></span></li>
<li class="MsoNormal"><span style="font-size: large;"><b><i>Floorplanning: </i></b><i>D</i></span><span style="font-size: large;">etermines the shapes and arrangement of subcircuit or modules, as well as the locations of external ports and IP or macro blocks.<o:p></o:p></span></li>
<li class="MsoNormal"><span style="font-size: large;"><b><i>Power and ground routing:</i></b><i> O</i></span><span style="font-size: large;">ften intrinsic to floorplanning, distributes power (</span><span style="font-size: large;"><i>VDD</i></span><span style="font-size: large;">) and ground (</span><span style="font-size: large;"><i>GND</i></span><span style="font-size: large;">) nets throughout the chip.<o:p></o:p></span></li>
<li class="MsoNormal"><span style="font-size: large;"><b><i>Placement</i></b><b>:</b></span><span style="font-size: large;"> Finds the spatial locations of all cells within each block.<o:p></o:p></span></li>
<li class="MsoNormal"><span style="font-size: large;"><b><i>Clock network synthesis</i></b><b>:</b></span><span style="font-size: large;"> Determines the buffering, gating (e.g., for power management) and routing of the clock signal to meet prescribed skew and delay requirements.<o:p></o:p></span></li>
<li class="MsoNormal"><span style="font-size: large;"><b><i>Global routing:</i></b><i> A</i></span><span style="font-size: large;">llocates routing resources that are used for connections; example resources include routing tracks in channels and in switchboxes.<o:p></o:p></span></li>
<li class="MsoNormal"><span style="font-size: large;"><b><i>Detailed routing:</i></b></span><span style="font-size: large;"> Assigns routes to specific metal layers and routing tracks within the global routing resourses<o:p></o:p></span></li>
<li class="MsoNormal"><span style="font-size: large;"><b><i>Timing Closure:</i></b></span><span style="font-size: large;"> Optimizes circuit performance by specialized placement and routing techniques.<br />
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<o:p></o:p></span></li>
</ul><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;">After detailed routing, </span><span style="font-size: large;"><i>electrically-accurate layout optimization </i></span><span style="font-size: large;">is performed at a small scale. Parasitic resistances (</span><span style="font-size: large;"><i>R</i></span><span style="font-size: large;">), capacitances (</span><span style="font-size: large;"><i>C</i></span><span style="font-size: large;">) and inductances (</span><span style="font-size: large;"><i>L</i></span><span style="font-size: large;">) are extracted from the completed layout, and then passed to timing analysis tools to check the functional behavior of the <a href="http://neeasic.blogspot.com/2011/03/yield-of-integrated-circuits.html">chip</a>. If the analyses reveal erroneous behavior or an insufficient design margin (guard band) against possible manufacturing and environmental variations, then incremental design optimizations are performed.<o:p></o:p></span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;"><br />
</span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;">The physical design of analog circuits deviates from the above methodology, which is geared primarily toward digital circuits. For analog physical design, the geometric representation of a circuit element is created using </span><span style="font-size: large;"><i>layout generators </i></span><span style="font-size: large;">or manual drawing. These generators only use circuit elements with known electrical parameters, such as the resistance of a resistor, and accordingly generate the appropriate geometric representation, e.g., a resistor layout with specified length and width.<o:p></o:p></span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;"><br />
</span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;"><b>Physical verification. </b></span><span style="font-size: large;">After physical design is completed, the layout must be fully verified to ensure correct electrical and logical functionality. Some problems found during physical verification can be tolerated if their impact on chip yield is negligible. In other cases, the layout must be changed, but these changes must be minimal and should not introduce new problems. Therefore, at this stage, layout changes are usually performed manually by experienced design engineers.<o:p></o:p></span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;"><br />
</span></div><ul style="font-family: Times,"Times New Roman",serif; margin-top: 0in;" type="disc"><li class="MsoNormal"><span style="font-size: large;"><i>Design rule checking </i></span><span style="font-size: large;">(</span><span style="font-size: large;"><i>DRC</i></span><span style="font-size: large;">) verifies that the layout meets all technology imposed constraints. DRC also verifies layer density for </span><span style="font-size: large;"><i>chemical-mechanical polishing </i></span><span style="font-size: large;">(</span><span style="font-size: large;"><i>CMP</i></span><span style="font-size: large;">).<o:p></o:p></span></li>
<li class="MsoNormal"><span style="font-size: large;"><i>Layout vs. schematic </i></span><span style="font-size: large;">(</span><span style="font-size: large;"><i>LVS</i></span><span style="font-size: large;">) checking verifies the functionality of the design. From the layout, a netlist is derived and compared with the original netlist produced from logic synthesis or circuit design.<o:p></o:p></span></li>
<li class="MsoNormal"><span style="font-size: large;"><i>Parasitic extraction </i></span><span style="font-size: large;">derives electrical parameters of the layout elements from their geometric representations; with the netlist, these are used to verify the electrical characteristics of the circuit.</span></li>
<li class="MsoNormal"><span style="font-size: large;"><i>Antenna rule checking </i></span><span style="font-size: large;">seeks to prevent </span><span style="font-size: large;"><i>antenna effects</i></span><span style="font-size: large;">, which may damage transistor gates during manufacturing plasma-etch steps through accumulation of excess charge on metal wires that are not connected to PN-junction nodes.</span></li>
<li class="MsoNormal"><span style="font-size: large;"><i>Electrical rule checking (ERC) </i></span><span style="font-size: large;">Verifies the correctness of power and ground connection, and that signal transition times (slew), capacitive loads and fanouts are appropriatelt bounded.<br />
<br />
</span></li>
</ul><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;">Both analysis and synthesis techniques are integral to the design of VLSI circuits. Analysis typically entails the modeling of circuit parameters and signal transitions, and often involves the solution of various equations using established numerical methods. The choice of algorithms for these tasks is relatively straightforward, compared to the vast possibilities for synthesis and optimization.</span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;"><br />
</span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;"><b>Fabrication:</b> The final DRC/LVS/ERC clean layout, usually represented in the GDSII stream format, is sent for manufacturing at a dedicated silicon foundry <i>(fab)</i>. The handoff o fthe design to the manufacturing process is called <b><i>tapeout</i></b>, even though data transmission from the design team to the silicon fab no longer relies on magnetic tape. Feneration of the data for manufacturing is sometimes referred to as <b><i>streaming out</i></b>, reflecting the use of GDSII Stream.</span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;"><br />
</span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;">As the fab, the design is patterned onto different layers using photolithographic process. Photomasks are used so that only certain patterns of silicon, specified by the layout, are exposed to a laser light source. Producing an IC requires many masks; modifying the design requires changes to some or all of the masks.</span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;"><br />
</span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;">ICs are manufactured on round silicon wafers with diameters ranging from 200mm(8 inches) to 300mm (12 inches). The ICs must then be tested and labeled as either <i>functional and defective</i>, sometimes according to bins depending on the functional or parametric (speed, power) tests that have failed. At the end of the manufacturing process, the ICs are separated, or diced, by sawing the wafer into smaller pieces.</span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;"><br />
</span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;"><b>Packaging and Testing:</b> After dicing, fuctional chips are typically packaged. Packaging is configured early in the design process, and reflects the application along with cost and form factor requirements. Package types include <i>DIPs, PGSs, BGAs</i> etc. After a die is positioned in the package cavity, its pins are connected to the package’s pins, eg., with wire bonding or solder bumps (<i>flip-chip</i>). The package is then sealed.</span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;"><br />
</span></div><div class="MsoNormal" style="font-family: Times,"Times New Roman",serif;"><span style="font-size: large;">After packaging, the finished product may be tested to ensure that it meets design requirements such as function, timing and power dissipation.</span></div></div>G. Partha Sarathihttp://www.blogger.com/profile/10982368947051776900noreply@blogger.com0tag:blogger.com,1999:blog-1074133253023786997.post-55254260837329099142011-03-14T01:54:00.000-07:002011-03-18T03:26:09.345-07:00VLSI Design Flow - 1<div dir="ltr" style="text-align: left;" trbidi="on"><table cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: 0px; margin-right: auto; text-align: left;"><tbody>
<tr><i><b><u><span style="color: black;"> VLSI Design Flow:</span></u></b></i><td style="text-align: center;"><br />
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</td><td style="text-align: center;"><img border="0" height="312" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjB6-S5XavcwQkkZ5AvSYmb71XkSmPl1ffNmCoskUy9pWEjw82zGPCpbZgykK63AsmKyM3euhS6e4NriU2v35387R6AfZfHU_Q_f8AQahqmcExwccTp7CbT723RhPY6xscR5mBC4SWWR7w/s400/VLSI+Design+Flow.bmp" style="margin-left: auto; margin-right: auto;" width="400" /></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Fig:1 VLSI Design Flow</td></tr>
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<div class="separator" style="clear: both; text-align: left;">The process of designing a very large-scale integrated (VLSI) circuit is highly complex. It can be separated into distinct steps (Fig. 1). Earlier steps are high-level; later design steps are at lower levels of abstraction. At the end of the process, before fabrication, tools and algorithms operate on detailed information about each circuit element’s geometric shape and electrical properties.</div><div class="separator" style="clear: both; text-align: left;"> </div><div class="separator" style="clear: both; text-align: left;"><b>System specification.</b> Chip architects, circuit designers, product marketers, operations managers, and layout and library designers collectively define the overall goals and high-level requirements of the system. These goals and requirements span functionality, performance, physical dimensions and production technology. Architectural design. A basic architecture must be determined to meet the system specifications. Example decisions are</div><ul style="text-align: left;"><li>Integration of analog and mixed-signal blocks</li>
<li>Memory management – serial or parallel – and the addressing scheme</li>
<li>Number and types of computational cores, such as processors and digital signal processing (DSP) units – and particular DSP algorithms</li>
<li>Internal and external communication, support for standard protocols, etc.</li>
<li>Usage of hard and soft intellectual-property (IP) blocks </li>
<li>Pinout, packaging, and the die-package interface</li>
<li>Power requirements </li>
<li> Choice of process technology and layer stacks</li>
</ul><b>Functional and logic design.</b> Once the architecture is set, the functionality and connectivity of each module (such as a processor core) must be defined. During functional design, only the high-level behavior must be determined. That is, each module has a set of inputs, outputs, and timing behavior.<br />
<br />
Logic design is performed at the register-transfer level (RTL) using a hardware description language (HDL) by means of programs that define the functional and timing behavior of a chip. Two common HDLs are Verilog and VHDL. HDL modules must be thoroughly simulated and verified.<br />
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Logic synthesis tools automate the process of converting HDL into low-level circuit elements. That is, given a Verilog or VHDL description and a technology library, a logic synthesis tool can map the described functionality to a list of signal nets or netlist, and specific circuit elements such as standard cells and transistors.<br />
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<b>Circuit design.</b> For the bulk of digital logic on the chip, the logic synthesis tool automatically converts Boolean expressions into what is referred to as a gate-level netlist, at the granularity of standard cells or higher. However, a number of critical, low-level elements must be designed at the transistor level; this is referred to as circuit design. Example elements that are designed at the circuit level include static<br />
RAM blocks, I/O, analog circuits, high-speed functions (multipliers), and electrostatic discharge (ESD) protection circuits. The correctness of circuit-level design is predominantly verified by circuit simulation tools such as SPICE. <br />
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<b>Physical design. </b>During physical design, all design components are instantiated with their geometric representations. In other words, all macros, cells, gates, transistors, etc., with fixed shapes and sizes per fabrication layer are assigned spatial locations (placement) and have appropriate routing connections (routing) completed in metal layers. The result of physical design is a set of manufacturing specifications that must subsequently be verified.<br />
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Continue to reading this article <a href="http://neeasic.blogspot.com/2011/03/vlsi-design-flow-2.html">here</a> </div>G. Partha Sarathihttp://www.blogger.com/profile/10982368947051776900noreply@blogger.com5tag:blogger.com,1999:blog-1074133253023786997.post-42114287108749925802010-06-23T09:33:00.000-07:002011-02-15T10:03:54.941-08:00CTS is Build for 4ns clock period. Is it work for 3ns and 4.5ns period clocks?Let us assume the CTS built with 4ns clock period clock have the following characterstics:<br />
Max. insertion delay = 1.2ns<br />
Max. skew = 300ps<br />
Max. transition = 400ps<br />
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If above values are ok for the 4.5ns and 3ns clock. Then the same clock three will work for the 4.5ns and 3ns. But it will not work for the 1ns clock as the insertion delay is more than the clock period.<br />
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<a target="_blank" href="http://www.amazon.com/Design-Essentials-Integrated-Circuits-Systems/dp/0387717129?ie=UTF8&tag=widgetsamazon-20&link_code=btl&camp=213689&creative=392969">Low Power Design Essentials (Integrated Circuits and Systems)</a><img src="http://www.assoc-amazon.com/e/ir?t=widgetsamazon-20&l=btl&camp=213689&creative=392969&o=1&a=0387717129" width="1" height="1" border="0" alt="" style="border:none !important; margin:0px !important; padding: 0px !important" />G. Partha Sarathihttp://www.blogger.com/profile/10982368947051776900noreply@blogger.com0