Floor Planning in P and R Flow - Part2

Continued from Part1


The Floorplanning is the first step in the ASIC P and R flow. The following terminologies are required to understand before proceeding further in to the Floorplanning process.

• Aspect Ratio of Core or Block or Design
• Standard Cell Rows
• RUF (Row Utilization Factor)
• Congestion
• Blockages – Placement and Routing
• Guide, Region and Fence

The major part of the Floorplanning is the Deciding the Chip/Block/Design size and placing the macros over the core area. Before proceeding into the Die size calculations understand the Die area and its components.

The die area is divided in to the following areas:

• Core area / Core Box
• IO area / IO Box
• Channel between the Core and IO area

The die consists of the number of IO pads and Corner pads in the IO area, and non or one or more Hard Macros (PLL, RAM, ROM, etc.) and Standard Cells (Flip Flops, NAND, NOR, AOI, etc.) in the core area.

The core logic consist the standard cells and had macros. The IO pads are the interfaces circuits between Core logic and the IO pins present on the IC package. The IC pins are used to connect and mount the IC on a PCB or board.

The core area is allotted for Macros and Standard Cells. The Standard Cell area is divided into the number of standard cell rows.

(Will be Continued in Part3.....Die Size Calculation)