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Wednesday, March 23, 2011

Floor Planning in P and R Flow

Floorplanning is the art of any physical design. A well thought-out floorplan leads to an ASIC design with optimum area  and high performance.

After importing the design into the P&R tools with all libraries and design netlist, floorplan is performed.

Floorplanning is nothing but placing the blocks /macros on the core area or another block after deciding the size of the block or core/die, thereby defining the standard cell areas between the macros/blocks.

We will create and develop a physical model of the design in the form of an initial optimized layout.

The following tasks are done during flooring planning.
1.      Deciding the size of the core/die or block
2.      Deciding the IO pads locations
3.      Placing the Macros at appropriate place on the core
4.      Placing any floorplan constrains like placement blockages, routing blockages, macro halos, etc., on the core area
5.      Fixing the placement of standard cells of particular module on the core area
6.      Deciding the continuous area for standard cell placement
The above tasks are performed based on the connectivity available in the netlist.

Optimization of the layout is in terms of reducing the chip area, reducing the total net length, improving the timing there by increasing the operating frequency, resolving congestion there by maximizing the routability, reducing the crosstalk noise effects, reducing the power consumption, etc.

To be continued in Part2.......

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