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Friday, March 18, 2011

VLSI Design Flow -2

Start reading from VLSI Design Flow -1 

Physical design is performed with respect to design rules that represent the physical limitations of the fabrication medium. For instance, all wires must be a prescribed minimum distance apart and have prescribed minimum width.  As such, the design layout must be recreated in (migrated to) each new manufacturing technology.

Physical design directly impacts circuit performance, area, reliability, power, and manufacturing yield. Examples of these impacts are discussed below.

  • Performance: long routes have significantly longer signal delays.
  • Area: placing connected modules far apart results in larger and slower chips.
  • Reliability: large number of vias can significantly reduce the reliability of the circuit.
  • Power: transistors with smaller gate lengths achieve greater switching speeds at the cost of higher leakage current and manufacturing variability; larger transistors and longer wires result in greater dynamic power dissipation.
  • Yield: wires routed too close together may decrease yield due to electrical shorts occurring during manufacturing, but spreading gates too far apart may also undermine yield due to longer wires and a higher probability of opens.

Due to its high complexity, physical design is split into several key steps:

  • Partitioning: Breaks up a circuit into smaller subcircuits or modules which can each be designed or analyzed individually.
  • Floorplanning: Determines the shapes and arrangement of subcircuit  or modules, as well as the locations of external ports and IP or macro blocks.
  • Power and ground routing: Often intrinsic to floorplanning, distributes power (VDD) and ground (GND) nets throughout the chip.
  • Placement: Finds the spatial locations of all cells within each block.
  • Clock network synthesis: Determines the buffering, gating (e.g., for power management) and routing of the clock signal to meet prescribed skew and delay requirements.
  • Global routing: Allocates routing resources that are used for connections; example resources include routing tracks in channels and in switchboxes.
  • Detailed routing: Assigns routes to specific metal layers and routing tracks within the global routing resourses
  • Timing Closure: Optimizes circuit performance by specialized placement and routing techniques.

After detailed routing, electrically-accurate layout optimization is performed at a small scale. Parasitic resistances (R), capacitances (C) and inductances (L) are extracted from the completed layout, and then passed to timing analysis tools to check the functional behavior of the chip. If the analyses reveal erroneous behavior or an insufficient design margin (guard band) against possible manufacturing and environmental variations, then incremental design optimizations are performed.

The physical design of analog circuits deviates from the above methodology, which is geared primarily toward digital circuits. For analog physical design, the geometric representation of a circuit element is created using layout generators or manual drawing. These generators only use circuit elements with known electrical parameters, such as the resistance of a resistor, and accordingly generate the appropriate geometric representation, e.g., a resistor layout with specified length and width.

Physical verification. After physical design is completed, the layout must be fully verified to ensure correct electrical and logical functionality. Some problems found during physical verification can be tolerated if their impact on chip yield is negligible. In other cases, the layout  must be changed, but these changes must be minimal and should not introduce new problems. Therefore, at this stage, layout changes are usually performed manually by experienced design engineers.

  • Design rule checking (DRC) verifies that the layout meets all technology imposed constraints. DRC also verifies layer density for chemical-mechanical polishing (CMP).
  • Layout vs. schematic (LVS) checking verifies the functionality of the design. From the layout, a netlist is derived and compared with the original netlist produced from logic synthesis or circuit design.
  • Parasitic extraction derives electrical parameters of the layout elements from their geometric representations; with the netlist, these are used to verify the electrical characteristics of the circuit.
  • Antenna rule checking seeks to prevent antenna effects, which may damage transistor gates during manufacturing plasma-etch steps through accumulation of excess charge on metal wires that are not connected to PN-junction nodes.
  • Electrical rule checking (ERC) Verifies the correctness of power and ground connection, and that signal transition times (slew), capacitive loads and fanouts are appropriatelt bounded.

Both analysis and synthesis techniques are integral to the design of VLSI circuits. Analysis typically entails the modeling of circuit parameters and signal transitions, and often involves the solution of various equations using established numerical methods. The choice of algorithms for these tasks is relatively straightforward, compared to the vast possibilities for synthesis and optimization.

Fabrication: The final DRC/LVS/ERC clean layout, usually represented in the GDSII stream format, is sent for manufacturing at a dedicated silicon foundry (fab). The handoff o fthe design to the manufacturing process is called tapeout, even though data transmission from the design team to the silicon fab no longer relies on magnetic tape. Feneration of the data for manufacturing is sometimes referred to as streaming out, reflecting the use of GDSII Stream.

As the fab, the design is patterned onto different layers using photolithographic process. Photomasks are used so that only certain patterns of silicon, specified by the layout, are exposed to a laser light source. Producing an IC requires many masks; modifying the design requires changes to some or all of the masks.

ICs are manufactured on round silicon wafers with diameters ranging from 200mm(8 inches) to 300mm (12 inches). The ICs must then be tested and labeled as either functional and defective, sometimes according to bins depending on the functional or parametric (speed, power) tests that have failed. At the end of the manufacturing process, the ICs are separated, or diced, by sawing the wafer into smaller pieces.

Packaging and Testing: After dicing, fuctional chips are typically packaged. Packaging is configured early in the design process, and reflects the application along with cost and form factor requirements. Package types include DIPs, PGSs, BGAs etc. After a die is positioned in the package cavity, its pins are connected to the package’s pins, eg., with wire bonding  or solder bumps (flip-chip). The package is then sealed.

After packaging, the finished product may be tested to ensure that it meets design requirements such as function, timing and power dissipation.

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