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Monday, March 14, 2011

VLSI Design Flow - 1

 VLSI Design Flow:




Fig:1 VLSI Design Flow


The process of designing a very large-scale integrated (VLSI) circuit is highly complex. It can be separated into distinct steps (Fig. 1). Earlier steps are high-level; later design steps are at lower levels of abstraction. At the end of the process, before fabrication, tools and algorithms operate on detailed information about each circuit element’s geometric shape and electrical properties.
 
System specification. Chip architects, circuit designers, product marketers, operations managers, and layout and library designers collectively define the overall goals and high-level requirements of the system. These goals and requirements span functionality, performance, physical dimensions and production technology. Architectural design. A basic architecture must be determined to meet the system specifications. Example decisions are
  • Integration of analog and mixed-signal blocks
  • Memory management – serial or parallel – and the addressing scheme
  • Number and types of computational cores, such as processors and digital signal processing (DSP) units – and particular DSP algorithms
  • Internal and external communication, support for standard protocols, etc.
  • Usage of hard and soft intellectual-property (IP) blocks 
  • Pinout, packaging, and the die-package interface
  • Power requirements
  • Choice of process technology and layer stacks
Functional and logic design. Once the architecture is set, the functionality and connectivity of each module (such as a processor core) must be defined. During functional design, only the high-level behavior must be determined. That is, each module has a set of inputs, outputs, and timing behavior.

Logic design is performed at the register-transfer level (RTL) using a hardware description language (HDL) by means of programs that define the functional and timing behavior of a chip. Two common HDLs are Verilog and VHDL. HDL modules must be thoroughly simulated and verified.

Logic synthesis tools automate the process of converting HDL into low-level circuit elements. That is, given a Verilog or VHDL description and a technology library, a logic synthesis tool can map the described functionality to a list of signal nets or netlist, and specific circuit elements such as standard cells and transistors.

Circuit design. For the bulk of digital logic on the chip, the logic synthesis tool automatically converts Boolean expressions into what is referred to as a gate-level netlist, at the granularity of standard cells or higher. However, a number of critical, low-level elements must be designed at the transistor level; this is referred to as circuit design. Example elements that are designed at the circuit level include static
RAM blocks, I/O, analog circuits, high-speed functions (multipliers), and electrostatic discharge (ESD) protection circuits. The correctness of  circuit-level design is predominantly verified by circuit simulation tools such as SPICE.

Physical design. During physical design, all design components are instantiated with their geometric representations. In other words, all macros, cells, gates, transistors, etc., with fixed shapes and sizes per fabrication layer are assigned spatial locations (placement) and have appropriate routing connections (routing) completed in metal layers. The result of physical design is a set of manufacturing specifications that must subsequently be verified.

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