Let us assume the CTS built with 4ns clock period clock have the following characterstics:
Max. insertion delay = 1.2ns
Max. skew = 300ps
Max. transition = 400ps
If above values are ok for the 4.5ns and 3ns clock. Then the same clock three will work for the 4.5ns and 3ns. But it will not work for the 1ns clock as the insertion delay is more than the clock period.
Low Power Design Essentials (Integrated Circuits and Systems)