Floor Planning in P and R Flow - Part2

Continued from Part1


The Floorplanning is the first step in the ASIC P and R flow. The following terminologies are required to understand before proceeding further in to the Floorplanning process.

• Aspect Ratio of Core or Block or Design
• Standard Cell Rows
• RUF (Row Utilization Factor)
• Congestion
• Blockages – Placement and Routing
• Guide, Region and Fence

The major part of the Floorplanning is the Deciding the Chip/Block/Design size and placing the macros over the core area. Before proceeding into the Die size calculations understand the Die area and its components.

The die area is divided in to the following areas:

• Core area / Core Box
• IO area / IO Box
• Channel between the Core and IO area

The die consists of the number of IO pads and Corner pads in the IO area, and non or one or more Hard Macros (PLL, RAM, ROM, etc.) and Standard Cells (Flip Flops, NAND, NOR, AOI, etc.) in the core area.

The core logic consist the standard cells and had macros. The IO pads are the interfaces circuits between Core logic and the IO pins present on the IC package. The IC pins are used to connect and mount the IC on a PCB or board.

The core area is allotted for Macros and Standard Cells. The Standard Cell area is divided into the number of standard cell rows.

(Will be Continued in Part3.....Die Size Calculation)

Floor Planning in P and R Flow

Floorplanning is the art of any physical design. A well thought-out floorplan leads to an ASIC design with optimum area  and high performance.

After importing the design into the P&R tools with all libraries and design netlist, floorplan is performed.

Floorplanning is nothing but placing the blocks /macros on the core area or another block after deciding the size of the block or core/die, thereby defining the standard cell areas between the macros/blocks.

We will create and develop a physical model of the design in the form of an initial optimized layout.

The following tasks are done during flooring planning.

1.      Deciding the size of the core/die or block

2.      Deciding the IO pads locations

3.      Placing the Macros at appropriate place on the core

4.      Placing any floorplan constrains like placement blockages, routing blockages, macro halos, etc., on the core area

5.      Fixing the placement of standard cells of particular module on the core area

6.      Deciding the continuous area for standard cell placement

The above tasks are performed based on the connectivity available in the netlist.

Optimization of the layout is in terms of reducing the chip area, reducing the total net length, improving the timing there by increasing the operating frequency, resolving congestion there by maximizing the routability, reducing the crosstalk noise effects, reducing the power consumption, etc.




To be continued in Part2.......